26 #ifndef DEVEMU_PCI_TYPE_CONFIG_H_
27 #define DEVEMU_PCI_TYPE_CONFIG_H_
31 #define NVME_TYPE_NAME "NVME Type"
33 #define PCI_TYPE_DEVICE_ID 0x6001
34 #define PCI_TYPE_VENDOR_ID 0x15b3
35 #define PCI_TYPE_SUBSYSTEM_ID 0x0051
36 #define PCI_TYPE_SUBSYSTEM_VENDOR_ID 0x15b3
37 #define PCI_TYPE_REVISION_ID 0
38 #define PCI_TYPE_CLASS_CODE 0x010802
63 #define PCI_TYPE_NUM_BAR_MEMORY_LAYOUT 2
83 #define PCI_TYPE_NUM_MSIX 4
84 #define PCI_TYPE_NUM_BAR_MSIX_TABLE_REGIONS 1
85 #define PCI_TYPE_NUM_BAR_MSIX_PBA_REGIONS 1
91 .start_address = 0x2000,
100 .start_address = 0x3000,
106 #define PCI_TYPE_NUM_BAR_DB_REGIONS 1
112 .region.start_address = 0x1000,
113 .region.size = (1 << 12),
121 #define PCI_TYPE_NUM_BAR_STATEFUL_REGIONS 1
122 #define PCI_TYPE_MAX_STATEFUL_REGION_SIZE 2048
128 .start_address = 0x0000,
doca_devemu_pci_bar_mem_type
According to the PCI specification a BAR that is mapped into Memory Space can define memory types.
@ DOCA_DEVEMU_PCI_BAR_MEM_TYPE_64_BIT
#define PCI_TYPE_NUM_BAR_MSIX_PBA_REGIONS
#define PCI_TYPE_NUM_BAR_MSIX_TABLE_REGIONS
static const struct bar_memory_layout_config layout_configs[PCI_TYPE_NUM_BAR_MEMORY_LAYOUT]
#define PCI_TYPE_NUM_BAR_MEMORY_LAYOUT
static const struct bar_db_region_config db_configs[PCI_TYPE_NUM_BAR_DB_REGIONS]
static const struct bar_region_config msix_pba_configs[PCI_TYPE_NUM_BAR_MSIX_PBA_REGIONS]
#define PCI_TYPE_NUM_BAR_DB_REGIONS
#define PCI_TYPE_NUM_BAR_STATEFUL_REGIONS
static const struct bar_region_config msix_table_configs[PCI_TYPE_NUM_BAR_MSIX_TABLE_REGIONS]
static const struct bar_region_config stateful_configs[PCI_TYPE_NUM_BAR_STATEFUL_REGIONS]
struct bar_region_config region
uint8_t log_db_stride_size
enum doca_devemu_pci_bar_mem_type memory_type