NVIDIA DOCA SDK Data Center on a Chip Framework Documentation
nvme_pci_type_config.h
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25 
26 #ifndef DEVEMU_PCI_TYPE_CONFIG_H_
27 #define DEVEMU_PCI_TYPE_CONFIG_H_
28 
29 #include <doca_devemu_pci_type.h>
30 
31 #define NVME_TYPE_NAME "NVME Type"
32 
33 #define PCI_TYPE_DEVICE_ID 0x6001
34 #define PCI_TYPE_VENDOR_ID 0x15b3
35 #define PCI_TYPE_SUBSYSTEM_ID 0x0051
36 #define PCI_TYPE_SUBSYSTEM_VENDOR_ID 0x15b3
37 #define PCI_TYPE_REVISION_ID 0
38 #define PCI_TYPE_CLASS_CODE 0x010802
39 
41  uint8_t bar_id;
42  uint16_t log_size;
44  uint8_t prefetchable;
45 };
46 
48  uint8_t bar_id;
49  uint64_t start_address;
50  uint64_t size;
51 };
52 
54  struct bar_region_config region;
55  uint8_t log_db_size;
57  bool with_data;
58  uint16_t db_id_msbyte;
59  uint16_t db_id_lsbyte;
60 };
61 
62 /* Configure how many BARs exist, and what they look like */
63 #define PCI_TYPE_NUM_BAR_MEMORY_LAYOUT 2
64 
66  [0] =
67  {
68  .bar_id = 0,
69  .log_size = 0xf,
71  .prefetchable = 0,
72  },
73  [1] =
74  {
75  .bar_id = 1,
76  .log_size = 0x0,
78  .prefetchable = 0,
79  },
80 };
81 
82 /* Configure how many MSI-X vectors there are, and where they are placed in the BAR */
83 #define PCI_TYPE_NUM_MSIX 4
84 #define PCI_TYPE_NUM_BAR_MSIX_TABLE_REGIONS 1
85 #define PCI_TYPE_NUM_BAR_MSIX_PBA_REGIONS 1
86 
88  [0] =
89  {
90  .bar_id = 0,
91  .start_address = 0x2000,
92  .size = (1 << 12),
93  },
94 };
95 
97  [0] =
98  {
99  .bar_id = 0,
100  .start_address = 0x3000,
101  .size = (1 << 12),
102  },
103 };
104 
105 /* Configure number of doorbells and regions and how they operate */
106 #define PCI_TYPE_NUM_BAR_DB_REGIONS 1
107 
109  [0] =
110  {
111  .region.bar_id = 0,
112  .region.start_address = 0x1000,
113  .region.size = (1 << 12),
114  .log_db_size = 0x2,
115  .log_db_stride_size = 0x2,
116  .with_data = false,
117  },
118 };
119 
120 /* Configure number of stateful regions and their ranges */
121 #define PCI_TYPE_NUM_BAR_STATEFUL_REGIONS 1
122 #define PCI_TYPE_MAX_STATEFUL_REGION_SIZE 2048
123 
125  [0] =
126  {
127  .bar_id = 0,
128  .start_address = 0x0000,
129  .size = (1 << 7),
130  },
131 };
132 
133 #endif // DEVEMU_PCI_TYPE_CONFIG_H_
doca_devemu_pci_bar_mem_type
According to the PCI specification a BAR that is mapped into Memory Space can define memory types.
@ DOCA_DEVEMU_PCI_BAR_MEM_TYPE_64_BIT
#define PCI_TYPE_NUM_BAR_MSIX_PBA_REGIONS
#define PCI_TYPE_NUM_BAR_MSIX_TABLE_REGIONS
static const struct bar_memory_layout_config layout_configs[PCI_TYPE_NUM_BAR_MEMORY_LAYOUT]
#define PCI_TYPE_NUM_BAR_MEMORY_LAYOUT
static const struct bar_db_region_config db_configs[PCI_TYPE_NUM_BAR_DB_REGIONS]
static const struct bar_region_config msix_pba_configs[PCI_TYPE_NUM_BAR_MSIX_PBA_REGIONS]
#define PCI_TYPE_NUM_BAR_DB_REGIONS
#define PCI_TYPE_NUM_BAR_STATEFUL_REGIONS
static const struct bar_region_config msix_table_configs[PCI_TYPE_NUM_BAR_MSIX_TABLE_REGIONS]
static const struct bar_region_config stateful_configs[PCI_TYPE_NUM_BAR_STATEFUL_REGIONS]
struct bar_region_config region
enum doca_devemu_pci_bar_mem_type memory_type